# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-unknown-unknown -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s

--- |
  define void @test_load_acquire_i8(i8* %addr) { ret void }
  define void @test_load_acquire_i16(i16* %addr) { ret void }
  define void @test_load_acquire_i32(i32* %addr) { ret void }
  define void @test_load_acquire_i64(i64* %addr) { ret void }
...
---

name:            test_load_acquire_i8
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: test_load_acquire_i8
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK: [[LDAXRB:%[0-9]+]]:gpr32 = LDAXRB [[COPY]] :: (volatile load (s8) from %ir.addr)
    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDAXRB]], %subreg.sub_32
    ; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
    ; CHECK: RET_ReallyLR implicit $x1
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (s8) from %ir.addr)
    $x1 = COPY %1
    RET_ReallyLR implicit $x1

...
---
name:            test_load_acquire_i16
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: test_load_acquire_i16
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK: [[LDAXRH:%[0-9]+]]:gpr32 = LDAXRH [[COPY]] :: (volatile load (s16) from %ir.addr)
    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDAXRH]], %subreg.sub_32
    ; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
    ; CHECK: RET_ReallyLR implicit $x1
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (s16) from %ir.addr)
    $x1 = COPY %1
    RET_ReallyLR implicit $x1

...
---
name:            test_load_acquire_i32
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: test_load_acquire_i32
    ; CHECK: liveins: $x0
    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK: [[LDAXRW:%[0-9]+]]:gpr32 = LDAXRW [[COPY]] :: (volatile load (s32) from %ir.addr)
    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64all = SUBREG_TO_REG 0, [[LDAXRW]], %subreg.sub_32
    ; CHECK: $x1 = COPY [[SUBREG_TO_REG]]
    ; CHECK: RET_ReallyLR implicit $x1
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (s32) from %ir.addr)
    $x1 = COPY %1
    RET_ReallyLR implicit $x1

...
---
name:            test_load_acquire_i64
alignment:       4
legalized:       true
regBankSelected: true
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: test_load_acquire_i64
    ; CHECK: [[COPY:%[0-9]+]]:gpr64sp = COPY $x0
    ; CHECK: [[LDAXRX:%[0-9]+]]:gpr64 = LDAXRX [[COPY]] :: (volatile load (s64) from %ir.addr)
    ; CHECK: $x1 = COPY [[LDAXRX]]
    ; CHECK: RET_ReallyLR implicit $x1
    %0:gpr(p0) = COPY $x0
    %1:gpr(s64) = G_INTRINSIC_W_SIDE_EFFECTS intrinsic(@llvm.aarch64.ldaxr), %0(p0) :: (volatile load (s64) from %ir.addr)
    $x1 = COPY %1
    RET_ReallyLR implicit $x1
